How to break through 3 nanometers down? Selective tungsten process to solve the major bottleneck of planar micro reduction
His is the first layer of circuit that links transistors with other circuits in the chip. With this innovative selective deposition technology, the contact resistance that affects transistor performance and increases power consumption can be reduced. In addition, with this technology, the node miniaturization and contacts of transistors can be reduced to 5 nm, 3 nm or even smaller, and chip power, performance and area / cost (PPAC) can be improved simultaneously.
Although the development of micro imaging technology can effectively reduce the size of transistor contact through holes, the traditional method of filling through holes with metal will seriously affect PPAC, Ying said. In the past, traditionally, transistor contacts were formed in a multi-layer manner. Firstly, the through-hole was lined with adhesive layer and titanium nitride barrier layer, then the core layer was produced by deposition technology, and then tungsten was used to fill the remaining space. Because of its low resistance coefficient, tungsten became the first choice of contact metal.
However, the 7-nm process technology has only 20 nm in diameter. The liner / barrier layer and nucleation layer account for 75% of the through-hole volume, and only 25% is used for tungsten. Thin tungsten wires have high contact resistance, which will seriously affect the effect of PPAC and 2D miniaturization. Therefore, Its new Endura Volta selective tungsten chemical vapor deposition system enables chip manufacturers to selectively deposit tungsten in the through-hole of the contact point of transistors, so as to eliminate the linear / barrier layer and nucleation layer. The whole through-hole will be filled with low resistance tungsten, and remove the bottleneck of subsequent PPAC.
It further pointed out that the selective tungsten deposition technology is an integrated material solution, which combines multiple process technologies in a pure and ultra-high vacuum environment, which is many times cleaner than the dust-free room itself. Atomic layer surface treatment can be applied to wafers. With a unique deposition process, tungsten atoms can be selectively deposited in the through-hole of the contact point, forming a perfect bottom-up filling without delamination, seamless and gap free.
